Ahmed Kamaleldin

Orcid: 0000-0002-7446-7741

According to our database1, Ahmed Kamaleldin authored at least 15 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoC.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2023
A Modular Platform for Adaptive Heterogeneous Many-Core Architectures.
PhD thesis, 2023

2022
AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors.
IEEE Access, 2022

An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core Systems.
Proceedings of the International Conference on Field-Programmable Technology, 2022

A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators.
IEEE Access, 2020

2019
Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

2018
Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Dynamically reconfigurable power efficient security for Internet of Things devices.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017
A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA.
Proceedings of the New Generation of CAS, 2017

A reconfigurable hardware platform implementation for software defined radio using dynamic partial reconfiguration on Xilinx Zynq FPGA.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


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