Ahmed Elkholy
Orcid: 0000-0002-3252-8585
According to our database1,
Ahmed Elkholy
authored at least 43 papers
between 2014 and 2022.
Collaborative distances:
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Bibliography
2022
A 3.2-GHz 405 fs<sub>rms</sub> Jitter -237.2 dB FoM<sub>JIT</sub> Ring-Based Fractional-N Synthesizer.
IEEE J. Solid State Circuits, 2022
2021
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling.
IEEE J. Solid State Circuits, 2021
A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
IEEE J. Solid State Circuits, 2020
A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques.
IEEE J. Solid State Circuits, 2020
Arabian horse identification based on whale optimised multi-class support vector machine.
Int. J. Comput. Appl. Technol., 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.
IEEE J. Solid State Circuits, 2019
A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.
IEEE J. Solid State Circuits, 2018
A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
A 0.0021 mm<sup>2</sup> 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
PhD thesis, 2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits, 2015
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Proceedings of the Symposium on VLSI Circuits, 2014
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014