Ahmed Abdelaal

Orcid: 0000-0001-9724-5896

According to our database1, Ahmed Abdelaal authored at least 10 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022

2021
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

FIR Filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
FIR DACs in CT Incremental Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Effective Filtering of Requantization Error in Dual Quantized CTDSM using FIR DAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019


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