Ahmed A. Morgan

Orcid: 0000-0003-3594-5250

According to our database1, Ahmed A. Morgan authored at least 16 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
On the accuracy of BLE indoor localization systems: An assessment survey.
Comput. Electr. Eng., 2024

2022
Improving emergency services efficiency during Islamic pilgrimage through optimal allocation of facilities.
Int. Trans. Oper. Res., 2022

2021
Using Bluetooth Low Energy for positioning systems within overcrowded environments: A real in-field evaluation.
Comput. Electr. Eng., 2021

2020
NoC<sup>2</sup>: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems.
IEEE Access, 2020

2019
Speeding up spatiotemporal feature extraction using GPU.
J. Real Time Image Process., 2019

2017
Introducing NoC<sup>2</sup>: Interconnecting NoC-based Systems through Ethernet.
Proceedings of the 14th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2017) / 12th International Conference on Future Networks and Communications (FNC 2017) / Affiliated Workshops, 2017

2016
An Enhanced Network-on-chip Simulation for Cluster-based Routing.
Proceedings of the 11th International Conference on Future Networks and Communications (FNC 2016) / The 13th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2016) / Affiliated Workshops, 2016

2015
Traffic analysis of multi-core body sensor networks based on Wireless NoC infrastructure.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

2013
Unified multi-objective mapping and architecture customisation of networks-on-chip.
IET Comput. Digit. Tech., 2013

2011
Improving Networks-on-Chip performability: A topology-based approach.
Int. J. Circuit Theory Appl., 2011

2010
Multi-objective optimization of NoC standard architectures using Genetic Algorithms.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010

Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Networks-on-chip topology optimization subject to power, delay, and reliability constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Power optimization for application-specific networks-on-chips: A topology-based approach.
Microprocess. Microsystems, 2009

2008
Power-aware topology optimization for networks-on-chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Application-specific networks-on-chip topology customization using network partitioning.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008


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