Ahmad A. Hiasat

Orcid: 0000-0002-4785-3698

According to our database1, Ahmad A. Hiasat authored at least 29 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

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Bibliography

2022
An arithmetic scaler circuit design for the expanded four-moduli set {2k-1, 2k+1, 22k+1, 22k}.
Comput. Electr. Eng., 2022

2020
A Scaler Design for the RNS Three-Moduli Set {2n+1-1, 2n, 2n-1} Based on Mixed-Radix Conversion.
J. Circuits Syst. Comput., 2020

2019
Sign Identifier for the Enhanced Three Moduli Set {2 n + k , 2 n - 1, 2 n+ 1 - 1}.
J. Signal Process. Syst., 2019

A Residue-to-Binary Converter with an Adjustable Structure for an Extended RNS Three-Moduli Set.
J. Circuits Syst. Comput., 2019

On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2n+k, 2n - 1, 2n+1 - 1}.
Comput. J., 2019

2018
Sign detector for the extended four-moduli set { 2<sup>n</sup> - 1 , 2<sup>n</sup> + 1 , 2<sup>2n</sup> + 1 , 2<sup>n + k</sup> }.
IET Comput. Digit. Tech., 2018

General modular adder designs for residue number system applications.
IET Circuits Devices Syst., 2018

New Residue Number System Scaler for the Three-Moduli Set {2<sup><i>n</i>+1</sup> - 1, 2<sup><i>n</i></sup>, 2<sup><i>n</i></sup> - 1}.
Comput., 2018

2017
A Residue-to-Binary Converter for the Extended Four-Moduli Set {2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>2n</sup>+1, 2<sup>2n+p</sup>}.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Efficient Reverse Converter for the Three-Moduli Set ( $ 2^{n+1}-1, 2^{n}, 2^{n}-1$ ).
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Efficient RNS Scalers for the Extended Three-Moduli Set (2<sup>n</sup>-1, 2<sup>n+p</sup>, 2<sup>n</sup>+1).
IEEE Trans. Computers, 2017

2016
A Sign Detector for a Group of Three-Moduli Sets.
IEEE Trans. Computers, 2016

2005
VLSI implementation of new arithmetic residue to binary decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
A Suggestion for a New RNS-Based Multiplier for a Family of Moduli.
Int. J. Comput. Their Appl., 2004

Limiter discriminator detection of narrow-band duobinary FSK in a land mobile channel.
Int. J. Commun. Syst., 2004

A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2<sup>n</sup> - (2<sup>p</sup> [plusmn] 1)).
Comput. J., 2004

2003
Residue number system to binary converter for the moduli set (2<sup>n-1</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1).
J. Syst. Archit., 2003

Bit-serial architecture for rank order and stack filters.
Integr., 2003

An arithmetic residue to binary conversion technique.
Integr., 2003

2002
High-Speed and Reduced-Area Modular Adder Structures for RNS.
IEEE Trans. Computers, 2002

2001
On the Theory of Error Control Based on Moduli with Common Factors.
Reliab. Comput., 2001

Semi-custom VLSI chip implementation of a new two-dimensional separable median filtering algorithm.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
New Efficient Structure for a Modular Multiplier for RNS.
IEEE Trans. Computers, 2000

1999
Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm.
Comput. J., 1999

Full-custom VLSI design of a new high-speed modular adder structures.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1997
Design and Implementation of An RNS Division Algorithmm.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996
Semi-custom VLSI design for RNS multipliers using combinational logic approach.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995
High-Speed Division Algorithm for Residue Number System.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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