Agustín Navarro-Torres

According to our database, Agustín Navarro-Torres authored at least 5 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Secure Prefetching for Secure Cache Systems.

Sumon Nath, Agustín Navarro-Torres, Alberto Ros, Biswabandan Panda

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

2023

BALANCER: bandwidth allocation and cache partitioning for multicore processors.

Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera

J. Supercomput., June, 2023

2022

Berti: an Accurate Local-Delta Data Prefetcher.

Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

Synchronization Strategies on Many-Core SMT Systems.

Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Maria Carpen-Amarie

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.

Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals

Proceedings of the Workshop on Computer Architecture Education, 2019