Adrian Wheeldon

Orcid: 0000-0003-4672-5990

According to our database1, Adrian Wheeldon authored at least 15 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
An Energy-Efficient Capacitive-RRAM Content Addressable Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

An Energy-efficient Capacitive-Memristive Content Addressable Memory.
CoRR, 2024

Design of Event-Driven Tsetlin Machines Using Safe Petri Nets.
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2024

2023
A multi-step finite-state automaton for arbitrarily deterministic Tsetlin Machine learning.
Expert Syst. J. Knowl. Eng., May, 2023

A study on the clusterability of latent representations in image pipelines.
Frontiers Neuroinformatics, March, 2023

An FPGA Architecture for Online Learning using the Tsetlin Machine.
CoRR, 2023

Energy-frugal and Interpretable AI Hardware Design using Learning Automata.
CoRR, 2023

2021
Low-Power Audio Keyword Spotting using Tsetlin Machines.
CoRR, 2021

Low-Latency Asynchronous Logic Design for Inference at the Edge.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Self-timed Reinforcement Learning using Tsetlin Machine.
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020
A Novel Multi-step Finite-State Automaton for Arbitrarily Deterministic Tsetlin Machine Learning.
Proceedings of the Artificial Intelligence XXXVII, 2020

Explainability and Dependability Analysis of Learning Automata based AI Hardware.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Self-timed, minimum latency circuits for the internet of things.
Integr., 2019

2017
Power proportional adder design for Internet of Things in a 65 nm process.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017


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