Adrian Kneip
Orcid: 0000-0002-3152-1947
According to our database1,
Adrian Kneip
authored at least 7 papers
between 2021 and 2024.
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Bibliography
2024
Bridging the hardware-software co-design gap in analog compute-in-memory accelerators towards edge CNN classification.
PhD thesis, 2024
2023
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm<sup>2</sup> CIM-SRAM With Multi-Bit Analog Batch-Normalization.
IEEE J. Solid State Circuits, 2023
2022
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021