Adrian Evans
Orcid: 0000-0002-2617-5007
According to our database1,
Adrian Evans
authored at least 33 papers
between 1998 and 2024.
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Bibliography
2024
Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey.
ACM Trans. Archit. Code Optim., June, 2024
City-Scale Multi-Camera Vehicle Tracking System with Improved Self-Supervised Camera Link Model.
CoRR, 2024
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405.
Proceedings of the IEEE European Test Symposium, 2024
A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024
2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF).
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
1998
Proceedings of the 35th Conference on Design Automation, 1998