Adrià Armejach

According to our database, Adrià Armejach authored at least 40 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

SpChar: Characterizing the sparse puzzle via decision trees.

Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó

J. Parallel Distributed Comput., 2024

GenArchBench: A genomics benchmark suite for arm HPC processors.

Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó

Future Gener. Comput. Syst., 2024

A Mess of Memory System Benchmarking, Simulation and Application Profiling.

Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Momeni, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard

CoRR, 2024

A Mess of Memory System Benchmarking, Simulation and Application Profiling.

Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Monemi, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Exploiting Vector Code Semantics for Efficient Data Cache Prefetching.

Francesc Martínez Palau, Martí Torrents, Adrià Armejach, Marc Casas

Proceedings of the 38th ACM International Conference on Supercomputing, 2024

2023

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor.

Rubén Langarita, Adrià Armejach, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó

IEEE ACM Trans. Comput. Biol. Bioinform., 2023

Characterization of a Coherent Hardware Accelerator Framework for SoCs.

Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Efficient Direct Convolution Using Long SIMD Instructions.

Alexandre de Limas Santana, Adrià Armejach, Marc Casas

Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2023

A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors.

Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations.

Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Alejandro Rico, Miquel Moretó

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi.

Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

A BF16 FMA is All You Need for DNN Training.

John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas

IEEE Trans. Emerg. Top. Comput., 2022

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.

Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó

IEEE ACM Trans. Comput. Biol. Bioinform., 2022

FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats.

John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas

Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2022

2021

On the use of many-core Marvell ThunderX2 processor for HPC workloads.

Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Miquel Moretó

J. Supercomput., 2021

Multilevel simulation-based co-design of next generation HPC microprocessors.

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau

Proceedings of the 2021 International Workshop on Performance Modeling, 2021

PLANAR: a programmable accelerator for near-memory data rearrangement.

Adrián Barredo, Adrià Armejach, Jonathan C. Beard, Miquel Moretó

Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator.

Guillem López-Paradís, Adrià Armejach, Miquel Moretó

Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training.

John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas

Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors.

Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Using Arm's scalable vector extension on stencil codes.

Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó

J. Supercomput., 2020

The gem5 Simulator: Version 20.0+.

Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian

CoRR, 2020

Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors.

John Osorio Ríos, Adrià Armejach, Gulrukh Khattak, Eric Petit, Sofia Vallecorsa, Marc Casas

Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

2019

Design trade-offs for emerging HPC processors based on mobile market technology.

Adrià Armejach, Marc Casas, Miquel Moretó

J. Supercomput., 2019

Design Space Exploration of Next-Generation HPC Machines.

Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas

Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

2018

Stencil codes on a vector length agnostic architecture.

Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2016

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.

Oriol Arcas-Abella, Adrià Armejach, Timothy Hayes, Gorker Alp Malazgirt, Oscar Palomar, Behzad Salami, Nehir Sönmez

Comput. Sci. Eng., 2016

MUSA: a multi-level simulation approach for next-generation HPC machines.

Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó

Proceedings of the International Conference for High Performance Computing, 2016

Implications of non-volatile memory as primary storage for database management systems.

Naveed Ul Mustafa, Adrià Armejach, Özcan Özturk, Adrián Cristal, Osman S. Unsal

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015

Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches.

Adrià Armejach, Adrián Cristal, Osman S. Unsal

Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015

2014

Techniques to improve concurrency in hardware transactional memory.

Adrià Armejach

PhD thesis, 2014

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.

Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song, John Mawer, Adrián Cristal, Mikel Luján

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Techniques to improve performance in requester-wins hardware transactional memory.

Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal

ACM Trans. Archit. Code Optim., 2013

HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory.

Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris

Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

2012

Circuit design of a dual-versioning L1 data cache.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

Integr., 2012

Novel SRAM bias control circuits for a low power L1 data cache.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Transactional prefetching: narrowing the window of contention in hardware transactional memory.

Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Circuit design of a dual-versioning L1 data cache for optimistic concurrency.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.

Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2009

EazyHTM: eager-lazy hardware transactional memory.

Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009