Adiwena Putra

Orcid: 0000-0001-6963-566X

According to our database¹, Adiwena Putra authored at least 3 papers between 2021 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2024

Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse.

[BibT_eX]

[DOI]

Prasetiyo

Adiwena Putra

Joo-Young Kim

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2021

Low Latency YOLOv3-Tiny Accelerator for Low-Cost FPGA Using General Matrix Multiplication Principle.

[BibT_eX]

[DOI]

IEEE Access, 2021

Adiwena Putra

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