Aditya Yanamandra

According to our database1, Aditya Yanamandra authored at least 8 papers between 2008 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
RAFT: A router architecture with frequency tuning for on-chip networks.
J. Parallel Distributed Comput., 2011

2010
On the Effects of Process Variation in Network-on-Chip Architectures.
IEEE Trans. Dependable Secur. Comput., 2010

Optimizing power and performance for reliable on-chip networks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

In-Network Caching for Chip Multiprocessors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A low-power phase change memory based hybrid cache architecture.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Analysis and solutions to issue queue process variation.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008


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