Aditya Jagirdar
According to our database1,
Aditya Jagirdar
authored at least 3 papers
between 2007 and 2010.
Collaborative distances:
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Bibliography
2010
Proceedings of the 2011 IEEE International Test Conference, 2010
2008
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007