Aditya Bansal
According to our database1,
Aditya Bansal
authored at least 25 papers
between 2004 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2024
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2024, 2024
2021
Whether the weather will help us weather the COVID-19 pandemic: Using machine learning to measure twitter users' perceptions.
Int. J. Medical Informatics, 2021
2016
Proceedings of the 12th IEEE International Conference on Control and Automation, 2016
2014
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
IEEE J. Solid State Circuits, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011
2009
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability.
Microelectron. Reliab., 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.
Proceedings of the 26th International Conference on Computer Design, 2008
2007
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 44th Design Automation Conference, 2007
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004