Aditya Anshul

Orcid: 0000-0001-6473-1417

According to our database1, Aditya Anshul authored at least 20 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches.
IEEE Des. Test, December, 2024

Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature.
SN Comput. Sci., October, 2024

Securing Reusable IP Cores Using Voice Biometric Based Watermark.
IEEE Trans. Dependable Secur. Comput., 2024

Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework.
IEEE Access, 2024

Robust Watermarking of Loop Unrolled Convolution Layer IP Design for CNN using 4-variable Encoded Register Allocation.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2023
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis.
Expert Syst. Appl., August, 2023

Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Comput. Electr. Eng., January, 2023

Exploring Handwritten Signature Image Features for Hardware Security.
IEEE Trans. Dependable Secur. Comput., 2023

Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis.
Microprocess. Microsystems, 2023

Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis.
Microprocess. Microsystems, 2023

Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters.
Proceedings of the International Conference on Microelectronics, 2023

Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration.
Proceedings of the International Conference on Microelectronics, 2023

Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems.
IEEE Consumer Electron. Mag., 2022

IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022


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