Adit D. Singh

Affiliations:
  • Auburn University, USA


According to our database1, Adit D. Singh authored at least 151 papers between 1978 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to defect based testing and test optimization in VLSI circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Innovative Practices Track: Session 2 Silent Data Corruption.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Silent Data Corruption from Timing Marginalities Due to Process Variations.
Proceedings of the IEEE European Test Symposium, 2024

2023
Silent Data Errors: Sources, Detection, and Modeling.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Silent Error Corruption: The New Reliability and Test Challenge.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

2022
A Systematic Bit Selection Method for Robust SRAM PUFs.
J. Electron. Test., 2022

Understanding Vmin Failures for Improved Testing of Timing Marginalities.
Proceedings of the IEEE International Test Conference, 2022

2021
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems.
J. Electron. Test., 2021

Estimating Operational Age of an Integrated Circuit.
J. Electron. Test., 2021

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020
Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices.
J. Electron. Test., 2020

A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
Proceedings of the IEEE International Test Conference, 2020

Exploring the Mysteries of System-Level Test.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Two-Pattern ∆IDDQ Test for Recycled IC Detection.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures.
Proceedings of the IEEE International Test Conference, 2019

Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

2018
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test.
IEEE Trans. Very Large Scale Integr. Syst., 2018

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging.
J. Electron. Test., 2017

A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Efficient SAT-based generation of hazard-activated TSOF tests.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Identifying high variability speed-limiting paths under aging.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Exploiting path delay test generation to develop better TDF tests for small delay defects.
Proceedings of the IEEE International Test Conference, 2017

Best paper.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Adaptive Test Methods for High IC Quality and Reliability.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Cell Aware and stuck-open tests.
Proceedings of the 21th IEEE European Test Symposium, 2016

Noise-Resilient SRAM Physically Unclonable Function Design for Security.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Testing cross wire opens within complex gates.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Special session: Hot topics: Statistical test methods.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

An Efficient Transition Detector Exploiting Charge Sharing.
Proceedings of the 28th International Conference on VLSI Design, 2015

Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs.
Proceedings of the 28th International Conference on VLSI Design, 2015

Scan based two-pattern tests: should they target opens instead of TDFs?
Proceedings of the 16th Latin-American Test Symposium, 2015

A Methodology for Identifying High Timing Variability Paths in Complex Designs.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Improving CMOS open defect coverage using hazard activated tests.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

On the testing of hazard activated open defects.
Proceedings of the 2014 International Test Conference, 2014

Error detection and recovery in better-than-worst-case timing designs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Detection conditions for errors in self-adaptive better-than-worst-case designs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Special session 4B: Elevator talks.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Current testing: Dead or alive?
Proceedings of the 18th IEEE European Test Symposium, 2013

Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Detection of gate-oxide defects with timing tests at reduced power supply.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

SEU Tolerant Robust Latch Design.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

SEU tolerant robust memory cell design.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011
Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

SSTKR: Secure and Testable Scan Design through Test Key Randomization.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An output compression scheme for handling X-states from over-clocked delay tests.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On Minimization of Test Application Time for RAS.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Test application time minimization for RAS using basis optimization of column decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Modified T-Flip-Flop based scan cell for RAS.
Proceedings of the 15th European Test Symposium, 2010

Adapting to adaptive testing.
Proceedings of the Design, Automation and Test in Europe, 2010

Distinguishing Resistive Small Delay Defects from Random Parameter Variations.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Modified Scan Flip-Flop for Low Power Testing.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Current Sensing Completion Detection for high speed and area efficient arithmetic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Output Hazard-Free Transition Delay Fault Test Generation.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Scan Delay Testing of Nanometer SoCs.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Scan cell design for launch-on-shift delay tests with slow scan enable.
IET Comput. Digit. Tech., 2007

Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Achieving high transition delay fault coverage with partial DTSFF scan chains.
Proceedings of the 2007 IEEE International Test Conference, 2007

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan.
Proceedings of the 16th Asian Test Symposium, 2007

2006
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI).
IEEE Trans. Very Large Scale Integr. Syst., 2006

Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.
J. Electron. Test., 2006

New JETTA Editors, 2006.
J. Electron. Test., 2006

Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction.
IEEE Des. Test Comput., 2006

Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable.
Proceedings of the 11th European Test Symposium, 2006

2005
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Pseudo Dual Supply Voltage Domino Logic Design.
J. Low Power Electron., 2005

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A self-timed structural test methodology for timing anomalies due to defects and process variations.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A random access scans architecture to reduce hardware overhead.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Low Voltage Test in Place of Fast Clock in DDSI Delay Test.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Delay Defect Characterization Using Low Voltage Test.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

T2: Statistical Methods for VLSI Test and Burn-in Optimization.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Low-power domino circuits using NMOS pull-up on off-critical paths.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Low-power dual V<sub>th</sub> pseudo dual V<sub>dd</sub> domino circuits.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Sizing CMOS Circuits for Increased Transient Error Tolerance.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits.
Proceedings of the 9th European Test Symposium, 2004

Reduce Yield Loss in Delay Defect Detection in Slack Interval.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Extending integrated-circuit yield-models to estimate early-life reliability.
IEEE Trans. Reliab., 2003

Multimode scan: Test per clock BIST for IP cores.
ACM Trans. Design Autom. Electr. Syst., 2003

Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Should Nanometer Circuits be Periodically Tested in the Field?
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Relating Yield Models to Burn-In Fall-Out in Time.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization".
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

IC Reliability Simulator ARET and Its Application in Design-for-Reliability.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Scan-Path with Directly Duplicated and Inverted Duplicated Registers.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Estimating burn-in fall-out for redundant memory.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Yield-Reliability Modeling for Fault Tolerant Integrated Circuits.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

1999
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.
J. Electron. Test., 1999

Testability evaluation of sequential designs incorporating the multi-mode scannable memory element.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
An IDDQ sensor for concurrent timing error detection.
IEEE J. Solid State Circuits, 1998

Binning for IC Quality: Experimental Studies on the SEMATECH Data.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
A differential built-in current sensor design for high-speed IDDQ testing.
IEEE J. Solid State Circuits, 1997

Incorporating <i>I</i><sub>DDQ</sub> Testing with BIST for Improved Coverage: An Experimental Study.
J. Electron. Test., 1997

Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
On the Effect of Defect Clustering on Test Transparency and IC Test Optimization.
IEEE Trans. Computers, 1996

1995
Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis.
IEEE Trans. Computers, 1995

An experimental evaluation of the differential BICS for I<sub>DDQ</sub> testing.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

I<sub>DDQ</sub> Testing of CMOS Opens: An Experimental Study.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

ADTS: an array defect-tolerance scheme for wafer scale gate arrays.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Incorporating IDDQ testing in BIST: improved coverage through test diversity.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1993
On optimizing VLSI testing for product quality using die-yield prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

The effect of defect clustering on test transparency and defect levels.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis.
Proceedings of the Digest of Papers: FTCS-23, 1993

1992
Analysis of the die test optimization algorithm for negative binomial yield statistics.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Chip Test Optimization Using Defect Clustering Information.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
A Modular Fault-Tolerant Binary Tree Architecture with Short Links.
IEEE Trans. Computers, 1991

On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue.
Computer, 1990

Fault Tolerance in VLSI Circuits.
Computer, 1990

1989
On Implementing Large Binary Tree Architectures in VLSI and WSI.
IEEE Trans. Computers, 1989

A single cached copy data coherence scheme for multiprocessor systems.
SIGARCH Comput. Archit. News, 1989

A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI.
Proceedings of the International Conference on Parallel Processing, 1989

An efficient channel routing algorithm for defective arrays.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Modelling correlated transient failures in fault-tolerant systems.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays.
IEEE Trans. Computers, 1988

A Highly Efficient Design for Reconfiguring the Processor Array in VLSI.
Proceedings of the International Conference on Parallel Processing, 1988

Near Optimal Embedding of Binary Tree Architecture in VLSI.
Proceedings of the 8th International Conference on Distributed Computing Systems, 1988

1987
On Area Efficient and Fault Tolerant Tree Embedding In VLSI.
Proceedings of the International Conference on Parallel Processing, 1987

1981
Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules.
IEEE Trans. Computers, 1981

1978
A simultaneous, radix four, I2L multiplier mechanized via repeated addition.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978


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