Adesh Garg

According to our database, Adesh Garg authored at least 14 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.

Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo-Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.

Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang, Afshin Momtaz

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2015

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.

Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz

IEEE J. Solid State Circuits, 2015

2014

A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.

Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao

IEEE J. Solid State Circuits, 2014

A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.

Adesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao

Proceedings of the Symposium on VLSI Circuits, 2014

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.

Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity.

Michael Boers, Iason Vassiliou, Saikat Sarkar, Sean T. Nicolson, Ehsan Adabi, Bagher Afshar, Bevin G. Perumana, Theodoros Chalvatzis, Spyros Kavadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Namik Kocaman, Adesh Garg, Hans Eberhart, Phil Yang, Hongyu Xie, Hea Joung Kim, Alireza Tarighat Mehrabani, David Garrett, Andrew J. Blanksby, Mong Kuan Wong, Durai Pandian Thirupathi, Siukai Mak, Radha Srinivasan, Amir Ibrahim, Ersin Sengul, Vincent Roussel, Po-Chao Huang, Tsuifang Yeh, Murat Mese, Jesus A. Castaneda, Brima Ibrahim, Tirdad Sowlati, Maryam Rofougaran, Ahmadreza Rofougaran

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.

Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications.

Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz

IEEE J. Solid State Circuits, 2011

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications.

Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber.

Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz

IEEE J. Solid State Circuits, 2010

2009

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber.

Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006

A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology.

Adesh Garg, Anthony Chan Carusone, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2006

2003

A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation.

Adesh Garg, Ian Steiner, Graham A. Jullien, James W. Haslett, G. H. McGibney

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003