Adel Baganne

According to our database1, Adel Baganne authored at least 26 papers between 1997 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2019
Low latency multicasting architecture implemented using new network topology.
Microprocess. Microsystems, 2019

2017
High-Level Implementation of a Chaotic and AES Based Crypto-System.
J. Circuits Syst. Comput., 2017

2016
Performance evaluation and design considerations of lightweight block cipher for low-cost embedded devices.
Proceedings of the 13th IEEE/ACS International Conference of Computer Systems and Applications, 2016

A Selective Encryption Scheme with Multiple Security Levels for the H.264/AVC Video Coding Standard.
Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

Efficient Hybrid Encryption System Based on Block Cipher and Chaos Generator.
Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

2015
A new approach for encryption system based on block cipher algorithms and logistic function.
Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

2012
Monitoring transaction level SystemC models using a generic and aspect-oriented framework.
Int. J. Comput. Aided Eng. Technol., 2012

2010
Design and Hardware Implementation of QoSS - AES Processor for Multimedia applications.
Trans. Data Priv., 2010

Performance evaluation of MIC@R NoC for real-time applications.
Int. J. Comput. Aided Eng. Technol., 2010

2009
Nouvelles architectures génériques de NoC.
Tech. Sci. Informatiques, 2009

2007
Constrained algorithmic IP design for system-on-chip.
Integr., 2007

MIC@R : A Generic Low Latency Router for On-Chip Networks.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Reconfigurable Implementation of the New Secure Hash Algorithm.
Proceedings of the The Second International Conference on Availability, 2007

2006
A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embed. Comput. Syst., 2006

2004
Co-simulation and communication synthesis approach for intellectual properties based SoCs.
Comput. Electr. Eng., 2004

A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Communication and Timing Constraints Analysis for IP Design and Integration.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A simulation based approach for incorporating virtual components IP cores into multimedia systems design.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration.
Proceedings of the 2003 Design, 2003

2002
A design methodology for IP integration.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

IP cores integration in DSP System-on-chip designs.
Proceedings of the 11th European Signal Processing Conference, 2002

A design methodology for integrating IP into SOC systems.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1999
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller.
J. VLSI Signal Process., 1999

Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1997
Hardware interface design for real time embedded systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997


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