Adam Teman
Orcid: 0000-0002-8233-4711
According to our database1,
Adam Teman
authored at least 81 papers
between 2008 and 2024.
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Bibliography
2024
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
IEEE Access, 2024
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach.
IEEE Access, 2023
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation.
IEEE Access, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
2022
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs.
CoRR, 2022
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification.
IEEE Access, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications.
CoRR, 2021
Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros.
IEEE Access, 2021
4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst., 2020
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Access, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An 800-MHz Mixed- V<sub>T</sub> 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications.
IEEE J. Solid State Circuits, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.
ACM Trans. Design Autom. Electr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Micro, 2017
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A low-power correlator for wakeup receivers with algorithm pruning through early termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Mitigating the impact of faults in unreliable memories for error-resilient applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE J. Solid State Circuits, 2014
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Microelectron. J., 2013
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel.
Sensors, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008