Adam Neale

Orcid: 0000-0001-5257-7694

According to our database1, Adam Neale authored at least 11 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2016
8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs.
PhD thesis, 2014

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011
Digitally programmable SRAM timing for nano-scale technologies.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2005
Interactive online tutorial assistance for a first programming course.
IEEE Trans. Educ., 2005


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