Adam Neale

According to our database, Adam Neale authored at least 11 papers between 2005 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs.

Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A Reliability Overview of Intel's 10+ Logic Technology.

Rohit Grover, Tony Acosta, C. AnDyke, Emre Armagan, C. Auth, Sunny Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, Gerald S. Leatherman, S.-H. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, Pinakpani Nayak, Adam Neale, D. Nminibapiel, Benjamin Orr, James Palmer, C. M. Pelto, S. S. Poon, I. Post, Tanmoy Pramanik, Anisur Rahman, Stephen Ramey, Norbert Seifert, K. Sethi, Anthony Schmitz, H. Wu, A. Yeoh

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup.

Bahar Ajdari, Samwel Sekwao, Ricardo Ascázubi, Adam Neale, Norbert Seifert

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.

Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2016

8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design.

Amr M. S. Tosson Abdelwahed, Adam Neale, Mohab H. Anis, Lan Wei

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs.

Adam Neale, Maarten Jonkman, Manoj Sachdev

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS.

Adam Neale, Manoj Sachdev

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs.

Adam Neale

PhD thesis, 2014

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC.

Adam Neale, Manoj Sachdev

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011

Digitally programmable SRAM timing for nano-scale technologies.

Adam Neale, Manoj Sachdev

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2005

Interactive online tutorial assistance for a first programming course.

Carol Hulls, Adam Neale, Ben Komalo, Val Petrov, David J. Brush

IEEE Trans. Educ., 2005