Adam B. Kinsman

According to our database1, Adam B. Kinsman authored at least 21 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
In-system constrained-random stimuli generation for post-silicon validation.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Design-for-Debug Architecture for Distributed Embedded Logic Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Automated Range and Precision Bit-Width Allocation for Iterative Computations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types.
IEEE Trans. Computers, 2011

Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses.
IEEE Trans. Computers, 2011

Numerical Data Representations for FPGA-Based Scientific Computing.
IEEE Des. Test Comput., 2011

2010
Time-Multiplexed Compressed Test of SOC Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies.
IEEE Trans. Haptics, 2010

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Robust design methods for hardware accelerators for iterative algorithms in scientific computing.
Proceedings of the 47th Design Automation Conference, 2010

2009
Computational bit-width allocation for operations in vector calculus.
Proceedings of the 27th International Conference on Computer Design, 2009

Finite Precision bit-width allocation using SAT-Modulo Theory.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Hardware-based parallel computing for real-time haptic rendering of deformable objects.
Proceedings of the 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2008

2006
Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels.
Proceedings of the 10th European Test Symposium, 2005

2004
Compressed Embedded Diagnosis of Logic Cores.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Embedded Compact Deterministic Test for IP-Protected Cores.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003


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