Achim Rettberg

Orcid: 0000-0002-9181-1110

Affiliations:
  • University of Oldenburg, Germany


According to our database1, Achim Rettberg authored at least 109 papers between 1999 and 2024.

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Bibliography

2024
Human-in-the-loop Reasoning For Traffic Sign Detection: Collaborative Approach Yolo With Video-llava.
CoRR, 2024

Hybrid Reasoning Based on Large Language Models for Autonomous Car Driving.
CoRR, 2024

Introduction to the Minitrack on Digital Twins: Platforms, Methods, Applications, and Impact.
Proceedings of the 57th Hawaii International Conference on System Sciences, 2024

2023
Introducing a group-based remote laboratory for embedded education.
Proceedings of the 21st IEEE International Conference on Industrial Informatics, 2023

2022
Key-Components for Digital Twin Modeling With Granularity: Use Case Car-as-a-Service.
IEEE Trans. Emerg. Top. Comput., 2022

Communication Layer Architecture for a Production Line Digital Twin Using Hierarchical Colored Petri Nets.
Proceedings of the Designing Modern Embedded Systems: Software, Hardware, and Applications, 2022

A methodology for creating semantic digital twin models supported by knowledge graphs.
Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022

2021
A Methodology for Digital Twin Modeling and Deployment for Industry 4.0.
Proc. IEEE, 2021

Deep Learning Classifiers for Automated Driving: Quantifying the Trained DNN Model's Vulnerability to Misclassification.
Proceedings of the 7th International Conference on Vehicle Technology and Intelligent Transport Systems, 2021

Enabling and supporting car-as-a-service by digital twin modeling and deployment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

On safety assurance case for deep learning based image classification in highly automated driving.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A digitalization concept for the interaction between users and car-as-a-service.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

A strategy for developing a pair of diverse deep learning classifiers for use in a 2-classifier system.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

2019
Ein Modellierungsansatz für eine Systemarchitekturbeschreibung von Automotive-Systemen mit MARTE und SysML.
Autom., 2019

German Hatespeech classification with Naive Bayes and Logistic Regression - hshl at GermEval 2019 - Task 2.
Proceedings of the 15th Conference on Natural Language Processing, 2019

Logistic Regression and Naive Bayes for Hierarchical Multi-label Classification at GermEval 2019 - Task 1.
Proceedings of the 15th Conference on Natural Language Processing, 2019

A Comparative Analysis Between SysML and AADL When Modeling a Real-Time System.
Proceedings of the Analysis, Estimations, and Applications of Embedded Systems, 2019

A Proposal to Trace and Maintain Requirements Constraints of Real-time Embedded Systems.
Proceedings of the Analysis, Estimations, and Applications of Embedded Systems, 2019

2018
Model-based requirements specification of real-time systems with UML, SysML and MARTE.
Softw. Syst. Model., 2018

Internet of Things Ontology for Digital Twin in Cyber Physical Systems.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Non-functional Constraints Annotation to Real-Time Embedded System Design.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

An Approach to Formalization of Architectural Viewpoints Design in Real-Time and Embedded Domain.
Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018

SPES Methodology and MARTE Constraints in Architectural Design.
Proceedings of the 2018 IEEE Symposium on Computers and Communications, 2018

Model-Based Design Methodology for Early Evaluation of Real-time and Embedded Constraints.
Proceedings of the 16th IEEE International Conference on Industrial Informatics, 2018

2017
Guidelines for using MARTE profile packages considering concerns of real-time embedded systems.
Proceedings of the 15th IEEE International Conference on Industrial Informatics, 2017

Applying MARTE Profile for Optimal Automotive System Specifications and Design.
Proceedings of the 50th Hawaii International Conference on System Sciences, 2017

A Model-Based Engineering Methodology for Requirements and Formal Design of Embedded and Real-Time Systems.
Proceedings of the 50th Hawaii International Conference on System Sciences, 2017

2016
SORT 2014.
Concurr. Comput. Pract. Exp., 2016

2015
State-based real-time analysis of SDF applications on MPSoCs with shared communication resources.
J. Syst. Archit., 2015

Towards Formalized Model-Based Requirements for a Seamless Design Approach in Safety-Critical Systems Development.
Proceedings of the 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2015

Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

2014
A program state machine based virtual processing model in SystemC.
SIGBED Rev., 2014

State-based scheduling analysis for distributed real-time systems - Coping with the large state space by a compositional approach.
Des. Autom. Embed. Syst., 2014

Impact analysis for timing requirements on real-time systems.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Autonomous Flight Control Meets Custom Payload Processing: A Mixed-Critical Avionics Architecture Approach for Civilian UAVs.
Proceedings of the 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014

Simulative evaluation of contract-based change management.
Proceedings of the 12th IEEE International Conference on Industrial Informatics, 2014

A model-based design space exploration for embedded image processing in industrial applications.
Proceedings of the 12th IEEE International Conference on Industrial Informatics, 2014

Evaluation of a state-based real-time scheduling analysis technique.
Proceedings of the 12th IEEE International Conference on Industrial Informatics, 2014

First results of automatic fault-injection in an AUTOSAR tool-chain.
Proceedings of the 12th IEEE International Conference on Industrial Informatics, 2014

2013
Hierarchical real-time scheduling in the multi-core era - An overview.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

Contracts for evolving systems.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

Reducing Re-verification Effort by Requirement-Based Change Management.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Contract-Based Compositional Scheduling Analysis for Evolving Systems.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Introduction to the Special Issue: SORT 2010.
Concurr. Comput. Pract. Exp., 2012

Abstraction Techniques for Compositional State-Based Scheduling Analysis.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Nicht-invasive Simulation des Energieverbrauchs von Hardware-Komponenten auf Systemebene mit SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems.
Proceedings of the 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2012

Towards a Rigorous Modeling Formalism for Systems of Systems.
Proceedings of the 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2012

2011
Ein generisches Treiber-Framework zur HW/SW-Kommunikation mittels OSSS-RMI.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Self-Reconfiguration for Fault-Tolerant FlexRay Networks.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Middleware Support for a Self-Configurable Wireless Sensor Network.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

2010
A Model-Based Design Methodology with Contracts to Enhance the Development Process of Safety-Critical Systems.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2010

Distributed Resource-Aware Scheduling for Multi-core Architectures with SystemC.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

Towards a synthesis semantics for systemC channels.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Autonomic Middleware for Automotive Embedded Systems.
Proceedings of the Autonomic Communication, 2010

2009
Run-time reconfigurable RTOS for reconfigurable systems-on-chip.
J. Embed. Comput., 2009

Modelling control systems in SystemC AMS - Benefits and limitations.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Overview of Multicore Requirements towards Real-Time Communication.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2009

Low-Level Space Optimization of an AES Implementation for a Bit-Serial Fully Pipelined Architecture.
Proceedings of the Analysis, 2009

Towards an Irritable Bowel Syndrome Control System Based on Artificial Neural Networks.
Proceedings of the Analysis, 2009

Towards a Load Balancing Middleware for Automotive Infotainment Systems.
Proceedings of the Analysis, 2009

Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Towards a Middleware Approach for a Self-configurable Automotive Embedded System.
Proceedings of the Software Technologies for Embedded and Ubiquitous Systems, 2008

Seamless design flow for reconfigurable systems.
Proceedings of the FPL 2008, 2008

Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Integrating Dynamic Load Balancing Strategies into the Car-Network.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Approach for a Formal Verification of a Bit-serial Pipelined Architecture.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Towards a Dynamically Reconfigurable Automotive Control System Architecture.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Prototyping an Ambient Light System - A Case Study.
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006

Integration of Energy Reduction into High-Level Synthesis by Partitioning.
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006

Communication-Aware Component Allocation Algorithm for a Hybrid Architecture.
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006

A new Design Partitioning Approach for Low Power High-Level Synthesis.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005
The Reconfigurable UML Machine Project Group.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

Towards Run-Time Partitioning of a Real Time Operating System for Reconfigurable Systems on Chip.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Spezielle Aspekte der Verlustleistungsgetriebenen High-Level Synthese.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

A Run-Time Partitioning Algorithm for RTOS on Reconfigurable Hardware.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.
Proceedings of the Embedded and Ubiquitous Computing, 2005

A Model-Based Approach for Executable Specifications on Reconfigurable Hardware.
Proceedings of the 2005 Design, 2005

A Y-Chart Based Tool for Reconfigurable System Design.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
A New High-Level Synthesis Approach of a Synchronous Bit-Serial Architecture.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Automatic Synthesis of SystemC-Code from Formal Specifications.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

Hardware Design and Protocol Specification for the Control and Communication within a Mechatronic System.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

A Self-Controlled and Dynamically Reconfigurable Architecture.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

Towards a Modular Communication System for FPGAs.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
From high-level Petri nets to SystemC.
Proceedings of the IEEE International Conference on Systems, 2003

Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems.
Proceedings of the 2003 Design, 2003

2002
How to integrate Webservices in Embedded System Design?.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002

Integration of Low Power Analysis into High-Level Scheduling in Distributed Real-Time Computing Systems.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002

Embedded System Design Based On Webservices.
Proceedings of the 2002 Design, 2002

2001
A Fast Asynchronous Re-Configurable Architecture for Multimedia Applications.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
The FLYSIG Prototyping Approach.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

The Specification Language SpecC within the PARADISE Design Environment.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

1999
The Re-Configurable Delay-Intensitive FLYSIG Architecture.
Proceedings of the Parallel and Distributed Processing, 1999


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