Abusaleh M. Jabir
According to our database1,
Abusaleh M. Jabir
authored at least 51 papers
between 2001 and 2024.
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Bibliography
2024
An AI-Assisted Connection Weight Prediction for Regression Testing of Integrated Circuits.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
2022
Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
2021
A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks.
J. Low Power Electron., 2019
The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
2018
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
2017
J. Low Power Electron., 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Learning method for ex-situ training of memristor crossbar based multi-layer neural network.
Proceedings of the 9th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops, 2017
2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2015
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
2013
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng., 2013
2012
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Simplified bit parallel systolic multipliers for special class of galois field (2<sup>m</sup>) with testability.
IET Comput. Digit. Tech., 2010
IET Comput. Digit. Tech., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
IET Comput. Digit. Tech., 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
GfXpress: A Technique for Synthesis and Optimization of GF(2<sup>m</sup>) Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Computers, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
2007
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers, 2007
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers, 2007
2006
An efficient technique for synthesis and optimization of polynomials in GF(2<sup><i>m</i></sup>).
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
Proceedings of the 2004 Design, 2004
2001
PhD thesis, 2001