Abir J. Mondal

According to our database, Abir J. Mondal authored at least 15 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ.

Kuntal Chakraborty, Abir J. Mondal

Integr., 2024

Design and Analysis of an Area and Power Efficient Programmable Delay Cell.

Kuntal Chakraborty, Jai Gopal Pandey, Abir J. Mondal

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.

Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder

Proceedings of the 33rd International Conference Radioelektronika, 2023

2022

Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current.

Mithilesh Kumar, Alak Majumder, Abir J. Mondal

J. Circuits Syst. Comput., 2022

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.

Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya

Integr., 2022

2021

A PVT aware differential delay circuit and its performance variation due to power supply noise.

Anirban Tarafdar, Abir J. Mondal, Uttam Kumar Bera, Bidyut K. Bhattacharyya

Integr., 2021

2019

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.

Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2017

A 65 nm Design of 0.6 V/8.98 <i>μ</i>W Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications.

Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya

J. Low Power Electron., 2017

A mathematical formulation to design and implementation of a low voltage swing transceiver circuit.

Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya

Integr., 2017

Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect.

Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya

Integr., 2017

A Design Methodology for MOS Current Mode Logic VCO.

Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.

Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016

A constraint driven technique for MOS amplifier design.

Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A method to design a comparator for sampled data processing applications.

Rama Prasad Acharya, Abir J. Mondal, Alak Majumder

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs.

Sandeep Kumar Singh, Abir J. Mondal, Alak Majumder

Proceedings of the 16th Latin-American Test Symposium, 2015