Abinash Mohanty

Orcid: 0000-0002-9916-478X

According to our database¹, Abinash Mohanty authored at least 15 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design.

[BibT_eX]

[DOI]

Anupreetham Anupreetham

ACM Trans. Reconfigurable Technol. Syst., March, 2024

2021

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.

[BibT_eX]

[DOI]

Anupreetham Anupreetham

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2019

A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches.

[BibT_eX]

[DOI]

CoRR, 2019

2018

Algorithm and Hardware Design for Efficient Deep Learning Inference.

[BibT_eX]

[DOI]

Abinash Mohanty

PhD thesis, 2018

Towards a Wearable Cough Detector Based on Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017

RTN in Scaled Transistors for On-Chip Random Seed Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

High-performance face detection with CPU-FPGA acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.

[BibT_eX]

[DOI]

Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014

Abinash Mohanty

Timeline

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