Abhoy Kole

Orcid: 0000-0002-2300-267X

According to our database1, Abhoy Kole authored at least 25 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

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Bibliography

2024
qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking.
CoRR, 2024

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits?
Proceedings of the Reversible Computation - 16th International Conference, 2024

Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Complete and Efficient Verification for a RISC-V Processor Using Formal Verification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Dynamic Realization of Multiple Control Toffoli Gate.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Impact of sneak paths on in-memory logic design in memristive crossbars.
it Inf. Technol., May, 2023

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures.
Proceedings of the Reversible Computation - 15th International Conference, 2023

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture.
Proceedings of the Reversible Computation - 15th International Conference, 2023

Verification of In-Memory Logic Design using ReRAM Crossbars.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

Mapping Quantum Circuits to 2-Dimensional Quantum Architectures.
Proceedings of the 52. Jahrestagung der Gesellschaft für Informatik, INFORMATIK 2022, Informatik in den Naturwissenschaften, 26., 2022

SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2020
Improved Mapping of Quantum Circuits to IBM QX Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018
A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Improved NCV Gate Realization of Arbitrary Size Toffoli Gates.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Test Pattern Generation Effort Evaluation of Reversible Circuits.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016
A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using N-Gate Lookahead.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2015
Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015


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