Abhishek Patyal
Orcid: 0000-0001-7094-7601
According to our database1,
Abhishek Patyal
authored at least 9 papers
between 2018 and 2023.
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Collaborative distances:
Timeline
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Bibliography
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
2021
ACM J. Emerg. Technol. Comput. Syst., 2021
2020
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2018
On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018