Abhishek Nag

According to our database, Abhishek Nag authored at least 9 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA.

Vivek Kumar Singh, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan

J. Circuits Syst. Comput., May, 2023

2022

Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks.

Vivek Kumar Singh, Abhishek Nag, Sambhu Nath Pradhan

Int. J. Embed. Syst., 2022

Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation.

Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan

J. Electron. Test., 2022

2020

Low power transistor level synthesis of finite state machines using a novel dual gating technique.

Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan

Int. J. Embed. Syst., 2020

2019

Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique.

Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan

J. Circuits Syst. Comput., 2019

2017

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating.

Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan

J. Circuits Syst. Comput., 2017

2016

An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning.

Abhishek Nag, Sambhu Nath Pradhan

J. Circuits Syst. Comput., 2016

2015

Layout-oriented look up table-based dual threshold approach to reduce leakage.

Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath

Int. J. Comput. Aided Eng. Technol., 2015

2014

Power gating architecture implementation inside clock period to reduce power.

Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan

Int. J. Comput. Aided Eng. Technol., 2014