Abhijit Sil

According to our database1, Abhijit Sil authored at least 5 papers between 2008 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm.
J. Circuits Syst. Comput., 2013

2012
Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

An energy-efficient 32-bit RISC processor for sensor platform in 90nm technology.
Proceedings of the International Conference on Energy Aware Computing, 2012

2011
A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm.
J. Low Power Electron., 2011

2008
High speed single-ended pseudo differential current sense amplifier for SRAM cell.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008


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