Abhijit Sil
According to our database1,
Abhijit Sil
authored at least 5 papers
between 2008 and 2013.
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Bibliography
2013
A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm.
J. Circuits Syst. Comput., 2013
2012
Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the International Conference on Energy Aware Computing, 2012
2011
A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm.
J. Low Power Electron., 2011
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008