Abhijit R. Asati
Orcid: 0000-0002-4914-5951Affiliations:
- Birla Institute Of Technology and Science (BITS), Pilani, India
According to our database1,
Abhijit R. Asati
authored at least 20 papers
between 2008 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis.
Wirel. Pers. Commun., 2022
J. King Saud Univ. Comput. Inf. Sci., 2022
2021
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm.
Microprocess. Microsystems, 2021
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications.
Circuits Syst. Signal Process., 2021
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications.
Comput. Intell., 2021
2020
Speed optimal FPGA implementation of the encryption algorithms for telecom applications.
Microprocess. Microsystems, 2020
High-Level synthesis assisted design and verification framework for automotive radar processors.
Microprocess. Microsystems, 2020
2018
Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation.
IET Image Process., 2018
2017
Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems.
Microprocess. Microsystems, 2017
Low-latency median filter core for hardware implementation of 5 × 5 median filtering.
IET Image Process., 2017
2016
A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images.
J. Electr. Comput. Eng., 2016
2015
Int. J. Reconfigurable Comput., 2015
Proceedings of the 2015 IEEE International Conference on Signal and Image Processing Applications, 2015
2014
Proceedings of the International Conference on Audio, 2014
2012
Proceedings of the International Symposium on Electronic System Design, 2012
2010
J. Signal Process. Syst., 2010
2009
Dual channel addition based FFT processor architecture for signal and image processing.
Int. J. High Perform. Syst. Archit., 2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009
2008
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008