Abhijit Dharchoudhury

According to our database, Abhijit Dharchoudhury authored at least 16 papers between 1992 and 1999.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

1999

Timing and Signal Integrity Analysis.

Steve M. Kang, Abhijit Dharchoudhury, David T. Blaauw, Stantanu Ganguly

Proceedings of the VLSI Handbook., 1999

A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.

Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.

Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw

Proceedings of the 36th Conference on Design Automation, 1999

1998

Emerging power management tools for processor design.

David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

CMOS Combinational Circuit Sizing by Stage-wise Tapering.

Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija

Proceedings of the 1998 Design, 1998

Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.

Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw

Proceedings of the 35th Conference on Design Automation, 1998

Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.

Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden

Proceedings of the 35th Conference on Design Automation, 1998

1997

Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.

Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Library-less synthesis for static CMOS combinational logic circuits.

Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.

Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang

Proceedings of the 33st Conference on Design Automation, 1996

1995

Worst-case analysis and optimization of VLSI circuit performances.

Abhijit Dharchoudhury, Sung-Mo Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994

Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.

Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Fast timing simulation of transient faults in digital circuits.

Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits.

Abhijit Dharchoudhury, Sung-Mo Kang

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis.

Abhijit Dharchoudhury, S. M. Kang

Proceedings of the Fifth International Conference on VLSI Design, 1992

An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits.

Abhijit Dharchoudhury, Sung-Mo Kang

Proceedings of the 29th Design Automation Conference, 1992