Abhijit Das

Orcid: 0000-0002-8912-9657

Affiliations:
  • Indian Institute of Technology Guwahati, Assam, India


According to our database1, Abhijit Das authored at least 20 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems - Overview, Challenges, and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Guest Editorial Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific, and Quantum Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators.
IEEE Trans. Computers, August, 2024

Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators.
CoRR, 2024

A MAC Protocol with Time Reversal for Wireless Networks within Computing Packages.
Proceedings of the 11th Annual ACM International Conference on Nanoscale Computing and Communication, 2024

2023
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

2022
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators.
CoRR, 2022

Revising NoC in Future Multicore-Based Consumer Electronics for Performance.
IEEE Consumer Electron. Mag., 2022

LOKI: A Hardware Trojan Affecting Multiple Components of an SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Designing Data-Aware Network-on-Chip for Performance.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty.
IEEE Trans. Computers, 2021

Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems.
CoRR, 2021

2020
SECTAR: Secure NoC using Trojan Aware Routing.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2018
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

2017
Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017


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