Abhijit Das
Orcid: 0000-0002-8912-9657Affiliations:
- Indian Institute of Technology Guwahati, Assam, India
According to our database1,
Abhijit Das
authored at least 19 papers
between 2017 and 2024.
Collaborative distances:
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Bibliography
2024
Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems - Overview, Challenges, and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024
Guest Editorial Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific, and Quantum Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators.
IEEE Trans. Computers, August, 2024
Proceedings of the 11th Annual ACM International Conference on Nanoscale Computing and Communication, 2024
2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
2022
CoRR, 2022
IEEE Consumer Electron. Mag., 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Computers, 2021
CoRR, 2021
2020
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
2017
Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017