Abhay S. Vidhyadharan

According to our database, Abhay S. Vidhyadharan authored at least 7 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2022

CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications.

Abhay S. Vidhyadharan, Sanjay Vidhyadharan

Wirel. Pers. Commun., 2022

High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters.

Abhay S. Vidhyadharan, Aiswarya Satheesh, Kilari Pragnaa, Sanjay Vidhyadharan

Circuits Syst. Signal Process., 2022

2021

A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM.

Abhay S. Vidhyadharan, Sanjay Vidhyadharan

Microelectron. J., 2021

An ultra-low-power CNFET based dual <i>V</i>_<i>DD</i> ternary dynamic Half Adder.

Abhay S. Vidhyadharan, Sanjay Vidhyadharan

Microelectron. J., 2021

CNFET-Based Ultra-Low-Power Dual-V_DD Ternary Half Adder.

Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan

Circuits Syst. Signal Process., 2021

2020

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC.

Sanjay Vidhyadharan, Surya Shankar Dan, Abhay S. Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad

Integr., 2020

2019

An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices.

Sanjay Vidhyadharan, Ramakant Ramakant, Abhay S. Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Surya Shankar Dan

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019