Abdellatif Bellaouar

According to our database1, Abdellatif Bellaouar authored at least 20 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Demonstration and Modelling of Excellent RF Switch Performance of 22nm FD-SOI Technology for Millimeter-Wave Applications.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

A 28GHz Sliding-IF Receiver in 22nm FDSOI.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A Low-Power, Compact 76-81GHz FMCW Transmitter for Automotive Radar in 22nm FDSOI.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2013
IIP2 requirements in 4G LTE handset receivers.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Novel analysis of passive mixer output impedance using switched-capacitor techniques.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Estimation of passive mixer output bandwidth using switched-capacitor techniques.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2006
A quad-band receiver for GSM/GPRS/EDGE in 90 nm digital CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
A quad-band GSM-GPRS transmitter with digital auto-calibration.
IEEE J. Solid State Circuits, 2004

2002
A 2 GHz CMOS even harmonic mixer for direct conversion receivers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
Low-power direct digital frequency synthesis for wireless communications.
IEEE J. Solid State Circuits, 2000

1999
CODEC for echo-canceling, full-rate ADSL modems.
IEEE J. Solid State Circuits, 1999

A low-power direct digital frequency synthesizer architecture for wireless communications.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1996
3.3-V BiCMOS current-mode logic circuits for high-speed adders.
IEEE J. Solid State Circuits, 1996

Circuit techniques for CMOS low-power high-performance multipliers.
IEEE J. Solid State Circuits, 1996

1995
Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime.
IEEE J. Solid State Circuits, June, 1995

Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects.
IEEE J. Solid State Circuits, June, 1995

A bootstrapped bipolar CMOS (B<sup>2</sup>CMOS) Gate for low-voltage applications.
IEEE J. Solid State Circuits, January, 1995

Circuit/architecture for low-power high-performance 32-bit adder.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling.
IEEE J. Solid State Circuits, June, 1994


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