Abdelkrim Kamel Oudjida

Orcid: 0000-0003-2923-7258

According to our database1, Abdelkrim Kamel Oudjida authored at least 20 papers between 2000 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2021
Radix-2<sup>w</sup> Arithmetic for Scalar Multiplication in Elliptic Curve Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Radix-2<sup> <i>r</i> </sup> recoding with common subexpression elimination for multiple constant multiplication.
IET Circuits Devices Syst., 2020

2018
Design of high-speed, low-power, and area-efficient FIR filters.
IET Circuits Devices Syst., 2018

Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses.
Comput. Sci. Rev., 2018

2017
H-RADIX a new heuristic for a single constant multiplication.
IET Circuits Devices Syst., 2017

A variable RADIX-2<sup>r</sup> algorithm for single constant multiplication.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016
Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
Radix-2<sup>r</sup> Arithmetic for Multiplication by a Constant: Further Results and Improvements.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Binary Arithmetic for Finite-Word-Length Linear Controllers : MEMS Applications. (Intégration sur électronique dédiée et embarquée du traitement du signal et de la commande pour les microsystemes appliqués à la microrobotique).
PhD thesis, 2014

Radix-2<sup>r</sup> Arithmetic for Multiplication by a Constant.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A new binary arithmetic for finite-word-length linear controllers: MEMS applications.
Proceedings of the 9th International Design and Test Symposium, 2014

2013
A New High Radix-2<sup>r</sup> (<i>r</i> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<i>N</i> ≥ 32) Multipliers.
J. Low Power Electron., 2013

2012
A new high radix-2<sup>r</sup> (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers.
SIGARCH Comput. Archit. News, 2012

A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier.
J. Low Power Electron., 2012

2011
High-Speed and Low-Power PID Structures for Embedded Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

2010
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2009
FPGA implementation of I<sup>2</sup>C & SPI protocols: A comparative study.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Universal Low/Medium Speed I<sup>2</sup>C-Slave Transceiver: a Detailed FPGA Implementation.
J. Circuits Syst. Comput., 2008

2001
N latency 2N I/O-bandwidth 2D-array matrix multiplication algorithm.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000


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