Abbas Sheibanyrad
According to our database1,
Abbas Sheibanyrad
authored at least 14 papers
between 2006 and 2017.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs.
IEEE Trans. Computers, 2013
2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011
Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
2008
Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures.
Integr., 2008
IEEE Des. Test Comput., 2008
2007
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
2006
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006