Aarti Gupta

Toby Walsh

Proceedings of the 8th International Conference on Learning Representations, 2020

Automating Modular Verification of Secure Information Flow.

[BibT_eX]

[DOI]

Lauren Pick

Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020

Verification of Recurrent Neural Networks for Cognitive Tasks via Reachability Analysis.

[BibT_eX]

[DOI]

Proceedings of the ECAI 2020 - 24th European Conference on Artificial Intelligence, 29 August-8 September 2020, Santiago de Compostela, Spain, August 29 - September 8, 2020, 2020

2019

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Lazy but Effective Functional Synthesis.

[BibT_eX]

[DOI]

Arie Gurfinkel

Tanakorn Leesatapornwongsa

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2019

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2019

FlyMC: Highly Scalable Testing of Complex Interleavings in Distributed Systems.

[BibT_eX]

[DOI]

Daniar Heri Kurniawan

Shan Lu

Haryadi S. Gunawi

Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

Lemma Synthesis for Automating Induction over Algebraic Data Types.

[BibT_eX]

[DOI]

Weikun Yang

Proceedings of the Principles and Practice of Constraint Programming, 2019

Functional Synthesis with Examples.

[BibT_eX]

[DOI]

Proceedings of the Principles and Practice of Constraint Programming, 2019

Quantified Invariants via Syntax-Guided Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 31st International Conference, 2019

2018

Model Checking Concurrent Programs.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Model Checking., 2018

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Control plane compression.

[BibT_eX]

[DOI]

Proceedings of the 2018 Conference of the ACM Special Interest Group on Data Communication, 2018

PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

A formal instruction-level GPU model for scalable verification.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification.

[BibT_eX]

[DOI]

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

Solving Constrained Horn Clauses Using Syntax and Data.

[BibT_eX]

[DOI]

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Lazy Self-composition for Security Verification.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 30th International Conference, 2018

Exploiting Synchrony and Symmetry in Relational Verification.

[BibT_eX]

[DOI]

Lauren Pick

Proceedings of the Computer Aided Verification - 30th International Conference, 2018

Syntax-Guided Termination Analysis.

[BibT_eX]

[DOI]

Yueling Zhang

Proceedings of the Computer Aided Verification - 30th International Conference, 2018

2017

A General Approach to Network Configuration Verification.

[BibT_eX]

[DOI]

Proceedings of the Conference of the ACM Special Interest Group on Data Communication, 2017

Trace-based Analysis of Memory Corruption Malware Attacks.

[BibT_eX]

[DOI]

Zhixing Xu

Proceedings of the Hardware and Software: Verification and Testing, 2017

2016

Parallel data race detection for task parallel programs with locks.

[BibT_eX]

[DOI]

Adarsh Yoga

Santosh Nagarakatte

Proceedings of the 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2016

Alive-FP: Automated Verification of Floating Point Based Peephole Optimizations in LLVM.

[BibT_eX]

[DOI]

David Menendez

Santosh Nagarakatte

Proceedings of the Static Analysis - 23rd International Symposium, 2016

2015

Scalable and scope-bounded software verification in Varvel.

[BibT_eX]

[DOI]

Autom. Softw. Eng., 2015

Assertion guided symbolic execution of multithreaded programs.

[BibT_eX]

[DOI]

Proceedings of the 2015 10th Joint Meeting on Foundations of Software Engineering, 2015

Completeness bounds and sequentialization for model checking of interacting firmware and hardware.

[BibT_eX]

[DOI]

Sunha Ahn

M. V. Achutha Kiran Kumar

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014

RTL2RTL Formal Equivalence: Boosting the Design Confidence.

[BibT_eX]

[DOI]

S. S. Bindumadhava

Proceedings of the Proceedings 2nd French Singaporean Workshop on Formal Methods and Applications, 2014

Environment-Sensitive Performance Tuning for Distributed Service Orchestration.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing for Computational Science - VECPAR 2014 - 11th International Conference, Eugene, OR, USA, June 30, 2014

Generating consistent updates for software-defined network configurations.

[BibT_eX]

[DOI]

Proceedings of the third workshop on Hot topics in software defined networking, 2014

ARC++: effective typestate and lifetime dependency analysis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Software Testing and Analysis, 2014

Formally Verifying Graphics FPU - An Intel® Experience.

[BibT_eX]

[DOI]

V. M. Achutha KiranKumar

Rajnish Ghughal

Proceedings of the FM 2014: Formal Methods, 2014

An Adaptable Rule Placement for Software-Defined Networks.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

ReproLite: A Lightweight Tool to Quickly Reproduce Hard System Bugs.

[BibT_eX]

[DOI]

Proceedings of the ACM Symposium on Cloud Computing, 2014

2013

Probabilistic Temporal Logic Falsification of Cyber-Physical Systems.

[BibT_eX]

[DOI]

Houssam Abbas

Georgios Fainekos

ACM Trans. Embed. Comput. Syst., 2013

Static analysis for concurrent programs with applications to data race detection.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2013

SETSUDŌ: perturbation-based testing framework for scalable distributed systems.

[BibT_eX]

[DOI]

Nadia Papakonstantinou

Proceedings of the First ACM SIGOPS Conference on Timely Results in Operating Systems, 2013

Feedback-directed unit test generation for C/C++ using concolic execution.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Software Engineering, 2013

2012

Introduction to special section on verification challenges in the concurrent world.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Donut Domains: Efficient Non-convex Domains for Abstract Interpretation.

[BibT_eX]

[DOI]

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2012

DTAM: dynamic taint analysis of multi-threaded programs for relevancy.

[BibT_eX]

[DOI]

Dongyoon Lee

Parasara Sridhar Duggirala

Proceedings of the 20th ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE-20), 2012

Efficient Probabilistic Model Checking of Systems with Ranged Probabilities.

[BibT_eX]

[DOI]

Khalil Ghorbal

Proceedings of the Reachability Problems - 6th International Workshop, 2012

Efficient predictive analysis for detecting nondeterminism in multi-threaded programs.

[BibT_eX]

[DOI]

Arnab Sinha

Proceedings of the Formal Methods in Computer-Aided Design, 2012

Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU.

[BibT_eX]

[DOI]

V. M. Achutha KiranKumar

Rajnish Ghughal

Proceedings of the Formal Methods in Computer-Aided Design, 2012

Object Model Construction for Inheritance in C++ and Its Applications to Program Analysis.

[BibT_eX]

[DOI]

Naveen Sharma

Proceedings of the Compiler Construction - 21st International Conference, 2012

Concurrent Test Generation Using Concolic Multi-trace Analysis.

[BibT_eX]

[DOI]

Proceedings of the Programming Languages and Systems - 10th Asian Symposium, 2012

2011

Symbolic predictive analysis for concurrent programs.

[BibT_eX]

[DOI]

Formal Aspects Comput., 2011

Predictive analysis for detecting serializability violations through Trace Segmentation.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

DC2: A framework for scalable, scope-bounded software verification.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011

BEST: A symbolic testing tool for predicting multi-threaded program failures.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011

Coverage guided systematic concurrency testing.

[BibT_eX]

[DOI]

Mahmoud Said

Proceedings of the 33rd International Conference on Software Engineering, 2011

Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2011

Modeling and Analyzing the Interaction of C and C++ Strings.

[BibT_eX]

[DOI]

Naoto Maeda

Rakesh Pothengil

Proceedings of the Formal Verification of Object-Oriented Software, 2011

Verifying concurrent programs: tutorial talk.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

Interprocedural Exception Analysis for C++.

[BibT_eX]

[DOI]

Proceedings of the ECOOP 2011 - Object-Oriented Programming, 2011

2010

Trace-Based Symbolic Analysis for Atomicity Violations.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2010

Program analysis via satisfiability modulo path programs.

[BibT_eX]

[DOI]

William R. Harris

Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2010

Numerical stability analysis of floating-point computations using software model checking.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Monte-carlo techniques for falsification of temporal properties of non-linear hybrid systems.

[BibT_eX]

[DOI]

Truong Nghiem

Proceedings of the 13th ACM International Conference on Hybrid Systems: Computation and Control, 2010

Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems.

[BibT_eX]

[DOI]

Edmund M. Clarke

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Scalable and precise program analysis at NEC.

[BibT_eX]

[DOI]

Nadia Papakonstantinou

Nishant Sinha

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009

Model checking sequential software programs via mixed symbolic analysis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Preface.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2009

Model Checking Concurrent Programs.

[BibT_eX]

[DOI]

Proceedings of the Verification, 2009

Semantic Reduction of Thread Interleavings in Concurrent Programs.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2009

Symbolic pruning of concurrent program executions.

[BibT_eX]

[DOI]

Proceedings of the 7th joint meeting of the European Software Engineering Conference and the ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2009

Robustness of Model-Based Simulations.

[BibT_eX]

[DOI]

Georgios Fainekos

Proceedings of the 30th IEEE Real-Time Systems Symposium, 2009

Symbolic Predictive Analysis for Concurrent Programs.

[BibT_eX]

[DOI]

Proceedings of the FM 2009: Formal Methods, 2009

Refining the control structure of loops using static analysis.

[BibT_eX]

[DOI]

Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008

Efficient SAT-based bounded model checking for software verification.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2008

Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Peephole Partial Order Reduction.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2008

Efficient Modeling of Concurrent Systems in BMC.

[BibT_eX]

[DOI]

Proceedings of the Model Checking Software, 2008

Modular verification of web services using efficient symbolic encoding and summarization.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2008

SLR: Path-Sensitive Analysis through Infeasible-Path Detection and Syntactic Language Refinement.

[BibT_eX]

[DOI]

Ou Wei

Proceedings of the Static Analysis, 15th International Symposium, 2008

Dynamic inference of likely data preconditions over predicates by tree learning.

[BibT_eX]

[DOI]

Swarat Chaudhuri

Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, 2008

Mining library specifications using inductive logic programming.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Software Engineering (ICSE 2008), 2008

Completeness in SMT-based BMC for Software Programs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Tunneling and slicing: towards scalable BMC.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Software Verification: Roles and Challenges for Automatic Decision Procedures.

[BibT_eX]

[DOI]

Proceedings of the Automated Reasoning, 4th International Joint Conference, 2008

Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions.

[BibT_eX]

[DOI]

Yu Yang

Ganesh Gopalakrishnan

Proceedings of the Automated Technology for Verification and Analysis, 2008

2007

SAT-Based Scalable Formal Verification Solutions

[BibT_eX]

[DOI]

Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-69167-1, 2007

Disjunctive image computation for software verification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic.

[BibT_eX]

[DOI]

Muralidhar Talupur

J. Satisf. Boolean Model. Comput., 2007

Synthesizing "Verification Aware" Models: Why and How?

[BibT_eX]

[DOI]

Akira Mukaiyama

Kazutoshi Wakabayashi

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Program Analysis Using Symbolic Ranges.

[BibT_eX]

[DOI]

Proceedings of the Static Analysis, 14th International Symposium, 2007

On the analysis of interacting pushdown systems.

[BibT_eX]

[DOI]

Proceedings of the 34th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2007

Using Ontologies and the Web to Learn Lexical Semantics.

[BibT_eX]

[DOI]

Tim Oates

Proceedings of the IJCAI 2007, 2007

Hybrid CEGAR: combining variable hiding and predicate abstraction.

[BibT_eX]

[DOI]

Hyondeuk Kim

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

From Hardware Verification to Software Verification: Re-use and Re-learn.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2007

Induction in CEGAR for Detecting Counterexamples.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Using Counterexamples for Improving the Precision of Reachability Computation with Polyhedra.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

Fast and Accurate Static Data-Race Detection for Concurrent Programs.

[BibT_eX]

[DOI]

Yu Yang

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

Efficient BMC for Multi-Clock Systems with Clocked Specifications.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Efficient distributed SAT and SAT-based distributed Bounded Model Checking.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2006

SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver.

[BibT_eX]

[DOI]

Muralidhar Talupur

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2006

SAT-Based Verification Methods and Applications in Hardware Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Hardware Verification, 2006

Static Analysis in Disjunctive Numerical Domains.

[BibT_eX]

[DOI]

Ilya Shlyakhter

Proceedings of the Static Analysis, 13th International Symposium, 2006

Mixed symbolic representations for model checking software programs.

[BibT_eX]

[DOI]

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

An Automata-Theoretic Approach for Model Checking Threads for LTL Propert.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE Symposium on Logic in Computer Science (LICS 2006), 2006

Accelerating high-level bounded model checking.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Disjunctive image computation for embedded software verification.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Predicate learning and selective theory deduction for a difference logic solver.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions.

[BibT_eX]

[DOI]

Nishant Sinha

Proceedings of the Computer Aided Verification, 18th International Conference, 2006

Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 18th International Conference, 2006

Whodunit? Causal Analysis for Counterexamples.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2006

2005

Verification Languages.

[BibT_eX]

[DOI]

Ali Alphan Bayazit

Yogesh S. Mahajan

Proceedings of the Embedded Systems Handbook., 2005

A survey of recent advances in SAT-based formal verification.

[BibT_eX]

[DOI]

Mukul R. Prasad

Armin Biere

Int. J. Softw. Tools Technol. Transf., 2005

Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Localization and Register Sharing for Predicate Abstraction.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination.

[BibT_eX]

[DOI]

Proceedings of the Logic for Programming, 2005

Model Checking C Programs Using F-SOFT.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Verification of Embedded Memory Systems using Efficient Memory Modeling.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Beyond safety: customized SAT-based model checking.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Symmetry Reduction in SAT-Based Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

Reasoning About Threads Communicating via Locks.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

F-Soft: Software Verification Platform.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

Verification Languages.

[BibT_eX]

Ali Alphan Bayazit

Yogesh S. Mahajan

Proceedings of the Industrial Information Technology Handbook, 2005

2004

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient Modeling of Embedded Memories in Bounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003

Iterative Abstraction using SAT-based BMC with Proof Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Learning from BDDs in SAT-based bounded model checking.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Abstraction and BDDs Complement SAT-Based BMC in DiVer.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 15th International Conference, 2003

2002

Assertion-based verification turns the corner.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Property-Specific Testbench Generation for Guided Simulation.

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Using complete-1-distinguishability for FSM equivalence checking.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Property-specific witness graph generation for guided simulation.

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Fast Error Diagnosis for Combinational Verification.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

SAT-Based Image Computation with Application in Reachability Analysis.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

1999

Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.

[BibT_eX]

[DOI]

Anand Raghunathan

Subhrajit Bhattacharya

Proceedings of the IEEE International Conference On Computer Design, 1999

Exploiting Retiming in a Guided Simulation Based Validation Methodology.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 1999

1998

Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Toward Formalizing a Validation Methodology Using Simulation Coverage.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1994

Tradeoffs in Canonical Sequential Function Representations.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993

Representation and symbolic manipulation of linearly inductive Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Parametric Circuit Representation Using Inductive Boolean Functions.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 5th International Conference, 1993

1992

Formal Hardware Verification Methods: A Survey.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1992

1990

Flexible Parallel Polygon Rendering.

[BibT_eX]

Proceedings of the 1990 International Conference on Parallel Processing, 1990

1986

A Parallel Computer Based on Cube-Connected Cycles for Wafer-Scale.

[BibT_eX]

Moon-Jung Chung

Edward J. Toy