Aaron C.-W. Liang

According to our database, Aaron C.-W. Liang authored at least 8 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs.

Sam M.-H. Hsiao, Amy H.-Y. Tsai, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen, Herming Chiueh

Proceedings of the IEEE International Test Conference, 2023

2022

A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules.

Aaron C.-W. Liang, Charles H.-P. Wen, Hsuan-Ming Huang

IEEE Trans. Very Large Scale Integr. Syst., 2022

SlewFTA: Functional Timing Analysis Considering Slew Propagation.

Zong-Hua Tsai, Aaron C.-W. Liang, Charles H.-P. Wen

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies.

Sam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen

Proceedings of the IEEE International Test Conference, 2022

Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability.

Jiun-Cheng Tsai, Aaron C.-W. Liang, Charles H.-P. Wen

Proceedings of the IEEE International Test Conference in Asia, 2022

2021

Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes.

Aaron C.-W. Liang, Hsuan-Ming Huang, Charles H.-P. Wen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions.

Denny C.-Y. Wu, Aaron C.-W. Liang, Charles H.-P. Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging.

Cheng-Hsien Shen, Aaron C.-W. Liang, Charles C.-H. Hsu, Charles H.-P. Wen

Proceedings of the IEEE International Test Conference, 2019