A. V. AnanthaLakshmi

According to our database, A. V. AnanthaLakshmi authored at least 5 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of eight.
• Erdős number of eight.

2017

Design of a reversible floating-point square root using modified non-restoring algorithm.

A. V. AnanthaLakshmi, Gnanou Florence Sudha

Microprocess. Microsystems, 2017

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications.

A. V. AnanthaLakshmi, Gnanou Florence Sudha

Microprocess. Microsystems, 2017

2015

Design of an efficient reversible single precision floating point adder.

A. V. AnanthaLakshmi, G. Florence Sudha

Int. J. Comput. Intell. Stud., 2015

2013

Transistor Representation of a Low-Power Reversible 32-Bit Comparator.

A. V. AnanthaLakshmi, G. Florence Sudha

Proceedings of the Intelligent Computing, 2013

2012

Design of a Novel Reversible Full Adder and Reversible Full Subtractor.

A. V. AnanthaLakshmi, G. Florence Sudha

Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012