A. R. Naseer

According to our database, A. R. Naseer authored at least 9 papers between 1993 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Two-way distributed sequential pattern mining using fruit fly algorithm along with Hadoop and map reduce framework.

V. Malsoru, A. R. Naseer, G. Narsimha

Int. J. Comput. Aided Eng. Technol., 2021

2007

WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs.

Ismat K. Maarouf, A. R. Naseer

Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006

SNARE: sensor node attached reputation evaluator.

Ismat K. Maarouf, A. R. Naseer

Proceedings of the 2006 ACM Conference on Emerging Network Experiment and Technology, 2006

1998

Direct mapping of RTL structures onto LUT-based FPGA's.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Optimal Clock Period for Synthesized Data Paths.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995

Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994

FAST: FPGA Targeted RTL Structure Synthesis Technique.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the Seventh International Conference on VLSI Design, 1994

An Efficient Technique for Mapping RTL Structures onto FPGAs.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the Field-Programmable Logic, 1994

1993

High Level Design Experiences with IDEAS.

C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer

Proceedings of the Sixth International Conference on VLSI Design, 1993