A. N. Nagamani

According to our database, A. N. Nagamani authored at least 10 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Hardware Security-present and Future Trends.

S. S. Rekha, A. N. Nagamani

Proceedings of the 2nd International Conference on Electronics and Electrical Engineering Technology, 2019

2018

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits.

A. N. Nagamani, S. N. Anuktha, N. Nanditha, Vinod Kumar Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Design of Optimized Reversible Squaring and Sum-of-Squares Units.

A. N. Nagamani, Chirag Ramesh, Vinod Kumar Agrawal

Circuits Syst. Signal Process., 2018

DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits.

A. N. Nagamani, Vijetha Ravichander, Madhumita Harish, Vinod Kumar Agrawal

Proceedings of the 2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018

2016

Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators.

A. N. Nagamani, S. Ashwin, B. Abhishek, K. V. Arjun, Vinod Kumar Agrawal

J. Circuits Syst. Comput., 2016

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits.

A. N. Nagamani, S. Ashwin, B. Abhishek, Vinod Kumar Agrawal

J. Electron. Test., 2016

Reversible Radix-4 booth multiplier for DSP applications.

A. N. Nagamani, R. Nikhil, Manish Nagaraj, Vinod Kumar Agrawal

Proceedings of the 2016 International Conference on Signal Processing and Communications (SPCOM), 2016

2015

Design of optimized reversible multiplier for high speed DSP application.

A. N. Nagamani, H. Vishnu Prasad, Rajendra S. Hathwar, Vinod Kumar Agrawal

Proceedings of the 10th International Conference on Information, 2015

2013

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder.

Himanshu Thapliyal, H. V. Jayashree, A. N. Nagamani, Hamid R. Arabnia

Trans. Comput. Sci., 2013

2011

Quaternary High Performance Arithmetic Logic Unit Design.

A. N. Nagamani, S. Nishchai

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011