A. Magalhaes-Lucas

According to our database, A. Magalhaes-Lucas authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications.

Daphnée Bosch, Abygaël Viey, Tadeu Mota Frutuoso, P. Lheritier, C. Licitra, N. Zerhouni, A. Albouy, Laurent Brunet, A. Magalhaes-Lucas, L. M. B. da Silva, H. Boutry, M. Husien Fahmy Taha Abdelrahman, F. Cristiano, R. Gassilloud, M. Ribotta, G. Romano, William Vandendaele, V. Benevent, M. Opprecht, S. Kerdilès, F. Milesi, F. Mazen, Benoit Sklénard, C. Euvrard-Colnat, Johannes Sturm, A. Lambert, C. Candebage, L. Laraignou, F. Boulard, A. Sarrazin, M. De Souza, Christoforos G. Theodorou, Xavier Garros, Perrine Batude

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory.

T. Dubreuil, Sylvain Barraud, J.-M. Pedini, Jean-Michel Hartmann, F. Boulard, A. Sarrazin, A. Gharbi, Johannes Sturm, A. Lambert, S. Martin, Niccolo Castellani, A. Anotta, A. Magalhaes-Lucas, Aurelie Souhaite, François Andrieu

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.

Tadeu Mota Frutuoso, Xavier Garros, Perrine Batude, Laurent Brunet, Joris Lacord, Benoit Sklénard, V. Lapras, Claire Fenouillet-Béranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, Edoardo Catapano, Mikaël Cassé, Jose Lugo-Alvarez, Philippe Ferrari, Fred Gaillard

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors.

Laurent Grenouillet, Niccolo Castellani, Alain Persico, Valentina Meli, Simon Martin, Olivier Billoint, R. Segaud, Stefania Bernasconi, C. Pellissier, Carine Jahan, Christelle Charpin-Nicolle, P. Dezest, Catherine Carabasse, Paul Besombes, Sebastien Ricavy, N. P. Tran, A. Magalhaes-Lucas, A. Roman, C. Boixaderas, Thomas Magis, Messaoud Bedjaoui, M. Tessaire, A. Seignard, F. Mazen, S. Landis, Elisa Vianello, Gabriel Molas, Fred Gaillard, Julien Arcamone, Etienne Nowak

Proceedings of the IEEE International Memory Workshop, 2021