A. Alper Goksoy

Orcid: 0000-0001-8679-9842

According to our database1, A. Alper Goksoy authored at least 16 papers between 2019 and 2024.

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Bibliography

2024
Runtime Monitoring of ML-Based Scheduling Algorithms Toward Robust Domain-Specific SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs).
IEEE Des. Test, February, 2024

Energy-Efficient and Communication-Aware Architectures for Accelerating Deep Learning Workloads.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Exploiting 2.5D/3D Heterogeneous Integration for AI Computing.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips.
ACM Trans. Embed. Comput. Syst., October, 2023

CANNON: Communication-Aware Sparse Neural Network Optimization.
IEEE Trans. Emerg. Top. Comput., 2023

Energy-Efficient On-Chip Training for Customized Home-based Rehabilitation Systems.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs.
IEEE Embed. Syst. Lett., 2022


Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2020
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework.
IEEE Trans. Computers, 2020

2019
Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips.
CoRR, 2019

A simulation framework for domain-specific system-on-chips: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019


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